Michael Jiayuan He (何嘉源)

CV

Research Scientist @ Meta
michaelhe at meta.com

About

I am a research scientist at Meta working on training efficiency and optimization on modern recommendation system (MRS).

I got PhD in computer science from University of Texas at Austin, under the guidance of Professor Keshav Pingali.

My research interests include parallel computing on multicore CPUs and GPUs, graph analytics and placement&routing in EDA. In general, I am interested in any techniques that accelerate programs.

I recevied my B.E. in Electrical Engineering and a second Bachelor in Economics from Tsinghua University in 2014.

Education

UT Autin, PhD in Computer Science, 2014 - 2022

Tsinghua University, B.E. in Microelectronics, 2010 - 2014

Tsinghua University, B.E. in Economics (second major), 2010 - 2014

Professional Experience

UT Austin, Research Assistant, 2014 - present

Facebook, Software Engineer Intern, May - Aug, 2020

VMware, Research Intern, May - Aug, 2018

Tsinghua University, Research Assistant, 2013 - 2014

Publications

  1. Jiayuan He , Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali. "SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity." IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 2022

  2. Jiayuan He , Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, and Rajit Manohar. "Interact: An Interactive Design Environment for Asynchronous Logic." Workshop on Open-Source EDA Technology (WOSET), November 2021.

  3. Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He , Sepideh Maleki, and Keshav Pingali. "An Open-Source EDA Flow for Asynchronous Logic." IEEE Design and Test 38, no. 2 (2021): 27-37.

  4. Udit Agarwal, Samira Ataei, Jiayuan He , Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. "A Digital Flow for Asynchronous VLSI Systems: Status Update. " Workshop on Open-Source EDA Technology (WOSET), November 2020.

  5. Jiayuan He , Yihang Yang, Rajit Manohar. "A power router for gridded cell placement." Workshop on Open-Source EDA Technology (WOSET), November 2020.

  6. Yihang Yang, Jiayuan He , and Rajit Manohar. "Dali: A gridded cell placement flow." Workshop on Open-Source EDA Technology (WOSET), November, 2020.

  7. Jiayuan He, Martin Burtscher, Rajit Manohar, and Keshav Pingali. "SPRoute: A Scalable Parallel Negotiation-based Global Router." In 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-8. IEEE, 2019. [PDF] [Github]

  8. Xin Xu, Na Zhang, Michael Cui, Jiayuan He, and Ridhi Surana. "Characterization and prediction of performance interference on mediated passthrough GPUs for interference-aware scheduler." In 11th {USENIX} Workshop on Hot Topics in Cloud Computing (HotCloud 19). 2019.[PDF]

  9. Samira Ataei, Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, and Rajit Manohar. "Toward a digital flow for asynchronous VLSI systems." In 2nd Workshop on Open-Source EDA Technology (WOSET), Westminster, CO, November 9, 2019.

  10. Yi-Shan Lu, Samira Ataei, Jiayuan He, Wenmian Hua, Sepideh Maleki, Yihang Yang, Martin Burtscher, Keshav Pingali, and Rajit Manohar. "Parallel Tools for Asynchronous VLSI Systems." In 1st Workshop on Open-Source EDA Technology (WOSET), San Diego, CA, November 8, 2018.

  11. Kuan Fang, Yufei Ni, Jiayuan He, Zonghui Li, Shuai Mu, and Yangdong Deng. "FastLanes: An FPGA accelerated GPU microarchitecture simulator." In 2013 IEEE 31st International Conference on Computer Design (ICCD), pp. 241-248. IEEE, 2013. (Best paper award)

Awards and Honors